1. Field of the Invention
The present invention is generally directed to the field of integrated circuits and semiconductor processing, and, more particularly, to a shallow trench antifuse formed in an integrated circuit device and methods of making and using same.
2. Description of the Related Art
A variety of different types of integrated circuit products are manufactured for use in a variety of different applications in today""s technology-driven society. For example, a variety of different types of logic devices, e.g., microprocessors, application-specific integrated circuits (xe2x80x9cASICsxe2x80x9d), etc., that are capable of executing a vast number of instructions per second are used in the control or operation of a variety of consumer products. Additionally, various types of memory devices, such as dynamic random-access memory devices (xe2x80x9cDRAMsxe2x80x9d), synchronous DRAMs (xe2x80x9cSDRAMsxe2x80x9d) and static random-access memory devices (xe2x80x9cSRAMsxe2x80x9d), are employed in many modern products, and such memory devices are capable of storing millions of bits of digital information.
It is a common practice in the semiconductor industry to design and implement semiconductor devices that are capable of being permanently programmed to exhibit different operational properties or characteristics depending upon a selection process performed at some point during manufacture or testing of the device. Such a practice is common in connection with the design and manufacture of semiconductor memory devices. For example, it is common for a semiconductor memory device to be designed such that, during or after the fabrication process, the manufacturer has the option of selecting one of a plurality of input/output (I/O) configurations for the device. A memory device having a nominal 64 megabit capacity may be configured to have one of several I/O configurations: for example, a 16 megabit-by-four-bit (xe2x80x9cxc3x974xe2x80x9d) I/O configuration, where each row and column address pair references four bits at a time, or a 8 megabit-by-eight-bit (xe2x80x9cxc3x978xe2x80x9d) I/O configuration, where each row and column address pair references eight bits at a time, or a 4 megabit-by-sixteen-bit (xe2x80x9cxc3x9716xe2x80x9d) configuration, where each row and column address pair references sixteen bits at a time. The selection of either the xc3x974, xc3x978, or the xc3x9716 I/O option commonly involves the actuation (xe2x80x9cblowingxe2x80x9d) of one or more one-time-programmable devices on the semiconductor device. Once the appropriate programmable devices are actuated, the device thereafter will permanently operate in accordance with the selected I/O configuration.
So-called xe2x80x9cantifusesxe2x80x9d are often used as one-time programmable devices in an integrated circuit product as a mechanism for changing the operating mode or configuration of the product. That is, antifuses are often used for the purpose of permitting the selection from among a plurality of programmable options for a semiconductor device. As those of ordinary skill in the art will appreciate, antifuses are essentially one-time programmable switching devices whose conductivity state (conductive or non-conductive) can be altered through application of predetermined programming signals or voltages to an integrated circuit""s I/O pins. Most commonly, an antifuse is initially (i.e., at the time of fabrication) xe2x80x9copenxe2x80x9d or non-conductive. If it is desired to actuate or xe2x80x9cblowxe2x80x9d a particular antifuse to change an operational characteristic of the integrated circuit, one or more predetermined programming voltages may be applied to the antifuse via the integrated circuit""s I/O pins. Once blown, the antifuse is rendered conductive. Further, once blown, it is typically not possible to reverse the programming. That is, once a fuse or antifuse has been blown, it cannot be un-blown.
Programmable options such as the I/O configuration of a memory device are often referred to as xe2x80x9cfuse optionsxe2x80x9d for the device. Those of ordinary skill in the art will appreciate that the I/O configuration of a memory device is but one example of the type of fuse options that may be available for a particular device. Fuse options may be available in connection with many different operational parameters of a semiconductor device, including, without limitation, the selection of certain internal timing parameters, the availability and activation of redundant rows or columns of memory cells in a memory device, the operational speed of a device, voltage regulation of a device, and so on. Providing a single semiconductor device with one or more fuse options is regarded as desirable, since a single design and fabrication process can be used to manufacture more than one class of end product. This flexibility eliminates the need for separate designs and separate fabrication processes to produce multiple classes of end product. Additionally, fuse options enable the manufacturer to counteract the effects of semiconductor process variations, advantageously increasing fabrication yield and maximizing production of higher-performance parts.
Antifuses may also be used to perform back end repairs of integrated circuits, i.e., repairs after the integrated circuit has been fabricated or packaged. Back end repairs of integrated circuits are typically accomplished by xe2x80x9cblowingxe2x80x9d antifuses to signal defective portions of the integrated circuit that they should be replaced with redundant circuits. For example, a row containing a defective memory cell in the array of a dynamic random access memory can be replaced with a redundant row of cells provided for that purpose.
Conventional antifuses may be similar in construction to capacitors in that they may include a pair of conductive plates separated by a dielectric or insulator material. Antifuses are typically characterized by the nature of the dielectric, which may be, for example, oxide, nitride or tantalum pentoxide. Antifuses are programmed or xe2x80x9cblownxe2x80x9d by applying a differential voltage between the plates that is sufficient to break down the dielectric, thereby establishing a conductive path between the conductive plates. Typically, this relatively high programming voltage is applied to the chip externally through terminals that are normally used for other purposes. For example, in a DRAM, a relatively high programming voltage may be applied to one of the data bit terminals after the integrated circuit has been placed in a programming mode by, for example, applying a predetermined combination of bits to other terminals of the integrated circuit.
The present invention is directed to an improved antifuse device and various methods that may solve, or at least reduce, some or all of the aforementioned problems.
The present invention is generally directed to a shallow trench antifuse and methods of making and using same. In one illustrative embodiment, the antifuse is comprised of an insulating layer positioned in the trench, a conductive member positioned above the insulating layer, at least a portion of the conductive member being positioned within the trench, the conductive member adapted to have at least one programming voltage applied thereto, and at least one doped active region formed in the substrate adjacent the trench. The antifuse further comprises at least one conductive contact coupled to the conductive member, and at least one conductive contact coupled to the doped active region. In further embodiments, the conductive member has an upper surface that is positioned below an upper surface of the substrate. In other embodiments, the conductive member has an upper surface that is positioned approximately planar with an upper surface of the substrate. In yet other embodiments, the conductive member has an upper surface that is positioned above an upper surface of the substrate. In various embodiments, the doped active region may surround the conductive member or the doped active region may be comprised of two separate, unconnected doped regions. In yet another illustrative embodiment, the doped active region is comprised of a single doped region positioned adjacent the trench.
The present invention is also directed to various methods. In one illustrative embodiment, the method comprises forming a trench in a semiconducting substrate, forming at least one layer of insulating material in the trench, forming a conductive member in the trench above the at least one layer of insulating material, forming at least one doped active region in the substrate adjacent the trench, forming at least one conductive contact that is coupled to the conductive member and forming at least one conductive contact that is coupled to the at least one doped active region. In further embodiments, the method further comprises applying a voltage to the conductive contact coupled to the doped active region and the conductive contact coupled to the conductive member to rupture the layer of insulating material and thereby establish a conductive path between the at least one doped active region and the conductive member. In even further embodiments, the method includes forming a first layer of insulating material, e.g., silicon dioxide, in the trench and then forming a layer of silicon nitride in the trench above the first layer of insulating material. A conductive member is then formed above the layer of silicon nitride.